1. Field of the Invention
The present invention relates to a semiconductor device, more particularly to an improved method of protecting a semiconductor device from the intrusion of moisture and contaminants through cracks.
2. Description of the Related Art
A plurality of semiconductor devices such as integrated circuits are commonly formed simultaneously on a semiconductor wafer, then separated into individual devices or xe2x80x98chips.xe2x80x99 Various measures are taken to protect the circuitry in the chips from damage by moisture and ionic contamination. The surfaces of the chips are generally protected by the deposition of an uppermost passivation layer. The edges of the chips are protected by the formation of a metal guard ring just inside the perimeter of each chip.
A problem with these protective measures is that the scribing or dicing process used to separate a wafer into chips can cause cracks in the edges of the passivation layer and other underlying layers. Such cracks may also arise from mechanical shock, caused by contact between two chips, for example. Once formed, such cracks have a tendency to propagate. If they reach the area inside the guard ring, moisture and contaminants infiltrating through the cracks can affect the chip circuitry, causing such problems as alteration of transistor characteristics, corrosion of metal interconnection wiring, and open circuits.
For this reason, it is a conventional practice to leave a margin of space between the chip circuitry and the edge of the chip, the margin being sufficiently wide that cracks propagating from the edges of the chip will usually stop short of the circuit area. It is also a conventional practice to inspect the chips for cracks after they have been separated from the wafer, and to reject chips that have cracks exceeding a certain size. The inspection is carried out visually, however, so it is time-consuming and expensive. It is also unreliable, because it is impractical to inspect all chips, and even in the chips that are inspected, it is difficult to detect all cracks exceeding the allowable size. Moreover, an innocuously small crack may propagate to a fatal size after the inspection process, when the chip is being sealed in resin inside its package. Contamination through cracks thus remains a significant cause of device failure.
Increased protection could be obtained by increasing the width of the unused margin at the chip edges, but this is not desirable. As advances in chip fabrication technology have made it possible to reduce the area occupied by the chip circuitry, in order to achieve a corresponding reduction in chip size, there is a need to decrease the width of the margin, rather than to increase this width.
A known method of preventing crack propagation is to form a slot in the passivation layer and the underlying inter-layer dielectric films, the slot being located between the guard ring and the edges of the chip, as disclosed, for example, in Japanese Laid Open Patent Publication No. 10-172927. This slot, however, has several disadvantages: it occupies further space in the margin outside the guard ring, thereby hindering the overall reduction of chip size; it provides a route by which moisture can reach the chip substrate; and metal plug material deposited in the slot during metalization steps in the fabrication process may come loose during or after the fabrication process and contaminate the semiconductor device, or other semiconductor devices, or equipment used to make and test these devices.
An object of the present invention is to provide a semiconductor device with improved protection from moisture and contaminants without increasing the size of the device.
Another object of the invention is to prevent contamination of the semiconductor device and its manufacturing equipment by loose metal material.
A semiconductor device according to the present invention is formed on a semiconductor chip. The device has a circuit area surrounded by a metal guard ring, and is covered by a passivation layer. The passivation layer has a slot formed above the guard ring, extending from the surface of the device down to the guard ring, surrounding the circuit area. The slot is preferably narrower than the guard ring and leaves the edges of the guard ring covered by the passivation layer.
The invention also provides a method of manufacturing a semiconductor device, including:
(a) forming an electronic circuit with metal interconnection wiring and a metal guard ring on a semiconductor chip;
(b) covering the electronic circuit and guard ring with a passivation layer; and
(c) forming a slot in the passivation layer above the guard ring.
Step (c) preferably includes the simultaneous formation of openings in the passivation layer for bonding pads.
In the invented semiconductor device, the slot prevents cracks in the passivation layer from propagating past the guard ring, thereby leaving the passivation layer able to protect the circuit area from moisture and contaminants. The guard ring prevents moisture and contaminants that enter the slot from reaching lower layers of the device. The size of the device can be reduced because the slot is disposed above the guard ring, instead of being disposed in the space between the guard ring and the edges of the device.
In the invented method of manufacturing a semiconductor device, no metal is deposited in the slot in the passivation layer, because the slot is formed after the guard ring and metal interconnection wiring. Accordingly, no metal material can come loose from the slot and contaminate the device or its manufacturing and testing equipment.